Power Dissipation Challenges in Multicore Floating-Point Units

Publication: Research - peer-reviewArticle in proceedings – Annual report year: 2010

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With increased densities on chips and the growing popularity of multicore processors and general-purpose graphics processing units (GPGPUs) power dissipation and energy consumption pose a serious challenge in the design of system-on-chips (SoCs) and a rise in costs for heat removal. In this work, we analyze the impact of power dissipation in floating-point (FP) units and we consider different alternatives in the implementation of FP-division that lead to substantial energy savings. We compare the implementation of division in a Fused Multiply-Add (FMA) unit based on the Newton-Raphson approximation algorithm to the implementation in a dedicated digit-recurrence unit. The results show a significant reduction of energy in a typical scientific application when the division digit-recurrence unit is used. In addition, we model the thermal behavior of the considered FP-units.
Original languageEnglish
Title of host publicationProceedings of 21st IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2010)
PublisherIEEE
Publication date2010
Pages257-264
ISBN (print)978-1-4244-6966-6
DOIs
StatePublished

Conference

Conference21st IEEE International Conference on Application-specific Systems, Architectures and Processors
Number21
CountryFrance
CityRennes
Period07/07/1009/07/10
Internet addresshttp://asap2010.inria.fr/
CitationsWeb of Science® Times Cited: No match on DOI
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