Post-placement temperature reduction techniques

Publication: Research - peer-reviewArticle in proceedings – Annual report year: 2010


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With technology scaled to deep submicron era, temperature and temperature gradient have emerged as important design criteria. We propose two post-placement techniques to reduce peak temperature by intelligently allocating whitespace in the hotspots. Both methods are fully compliant with commercial technologies, and can be easily integrated with state-of-the-art thermal-aware design flow. Experiments in a set of tests on circuits implemented in STM 65nm technologies show that our methods achieve better peak temperature reduction than directly increasing circuit's area.
Original languageEnglish
Title of host publicationDesign, Automation & Test in Europe Conference & Exhibition (DATE), 2010
Publication date2010
ISBN (print)978-1-4244-7054-9
StatePublished - 2010


ConferenceDesign, Automation & Test in Europe Conference & Exhibition (DATE), 2010
Period01/01/2010 → …

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