Improving Performance of Software Implemented Floating Point Addition

Publication: Research - peer-reviewArticle in proceedings – Annual report year: 2011

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We outline and evaluate hardware extensions to an integer processor pipeline which allow IEEE 754 oating point, FP, addition to be eciently implemented in software. With a very moderate increase in hardware resources, our perfor- mance evaluation shows that, for a benchmark that executes 12.5% FP addition instructions, our approach exhibits a rel- ative slowdown of 3.38 to 15.15 as compared to dedicated hardware. This is a signicant improvement of pure software emulation which leads to relative slowdowns up to 45.33.
Original languageEnglish
Title of host publicationProceedings of the Fourth Swedish Workshop on Multicore Computing
Publication date2011
StatePublished - 2011
Peer-reviewedYes

Workshop

Workshop4th Swedish Workshop on Multicore Computing
Number4
CountrySweden
CityLinköping
Period23/11/201125/11/2011
Internet addresshttp://www.ida.liu.se/conferences/mcc2011/
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