Execution models for processors and instructions

Publication: Research - peer-reviewArticle in proceedings – Annual report year: 2010

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Execution models for processors and instructions. / Brandner, Florian; Pavlu, Viktor; Krall, Andreas.

NORCHIP, 2010. IEEE Computer Society Press, 2010. p. 1-4.

Publication: Research - peer-reviewArticle in proceedings – Annual report year: 2010

Harvard

Brandner, F, Pavlu, V & Krall, A 2010, 'Execution models for processors and instructions'. in NORCHIP, 2010. IEEE Computer Society Press, pp. 1-4., 10.1109/NORCHIP.2010.5669478

APA

Brandner, F., Pavlu, V., & Krall, A. (2010). Execution models for processors and instructions. In NORCHIP, 2010. (pp. 1-4). IEEE Computer Society Press. 10.1109/NORCHIP.2010.5669478

CBE

Brandner F, Pavlu V, Krall A. 2010. Execution models for processors and instructions. In NORCHIP, 2010. IEEE Computer Society Press. pp. 1-4. Available from: 10.1109/NORCHIP.2010.5669478

MLA

Vancouver

Brandner F, Pavlu V, Krall A. Execution models for processors and instructions. In NORCHIP, 2010. IEEE Computer Society Press. 2010. p. 1-4. Available from: 10.1109/NORCHIP.2010.5669478

Author

Brandner, Florian; Pavlu, Viktor; Krall, Andreas / Execution models for processors and instructions.

NORCHIP, 2010. IEEE Computer Society Press, 2010. p. 1-4.

Publication: Research - peer-reviewArticle in proceedings – Annual report year: 2010

Bibtex

@inbook{a429e58315c44233b86feb163590787f,
title = "Execution models for processors and instructions",
publisher = "IEEE Computer Society Press",
author = "Florian Brandner and Viktor Pavlu and Andreas Krall",
year = "2010",
doi = "10.1109/NORCHIP.2010.5669478",
isbn = "978-1-4244-8972-5",
pages = "1-4",
booktitle = "NORCHIP, 2010",

}

RIS

TY - GEN

T1 - Execution models for processors and instructions

A1 - Brandner,Florian

A1 - Pavlu,Viktor

A1 - Krall,Andreas

AU - Brandner,Florian

AU - Pavlu,Viktor

AU - Krall,Andreas

PB - IEEE Computer Society Press

PY - 2010

Y1 - 2010

N2 - Modeling the execution of a processor and its instructions is a challenging problem, in particular in the presence of long pipelines, parallelism, and out-of-order execution. A naive approach based on finite state automata inevitably leads to an explosion in the number of states and is thus only applicable to simple minimalistic processors. During their execution, instructions may only proceed forward through the processor's datapath towards the end of the pipeline. The state of later pipeline stages is thus independent of potential hazards in preceding stages. This also applies for data hazards, i.e., we may observe data by-passing from a later stage to an earlier one, but not in the other direction. Based on this observation, we explore the use of a series of parallel finite automata to model the execution states of the processor's resources individually. The automaton model captures state updates of the individual resources along with the movement of instructions through the pipeline. A highly-flexible synchronization scheme built into the automata enables an elegant modeling of parallel computations, pipelining, and even out-of-order execution. An interesting property of our approach is the ability to model a subset of a given processor using a sub-automaton of the full execution model.<br /> Keyword: pipeline processing,Automata,automata theory,instruction sets,finite state automata,parallel finite automata,Synchronization,Program processors,instruction set,highly flexible synchronization scheme,Computational modeling,out-of-order execution,Hazards,parallel processing,Pipelines

AB - Modeling the execution of a processor and its instructions is a challenging problem, in particular in the presence of long pipelines, parallelism, and out-of-order execution. A naive approach based on finite state automata inevitably leads to an explosion in the number of states and is thus only applicable to simple minimalistic processors. During their execution, instructions may only proceed forward through the processor's datapath towards the end of the pipeline. The state of later pipeline stages is thus independent of potential hazards in preceding stages. This also applies for data hazards, i.e., we may observe data by-passing from a later stage to an earlier one, but not in the other direction. Based on this observation, we explore the use of a series of parallel finite automata to model the execution states of the processor's resources individually. The automaton model captures state updates of the individual resources along with the movement of instructions through the pipeline. A highly-flexible synchronization scheme built into the automata enables an elegant modeling of parallel computations, pipelining, and even out-of-order execution. An interesting property of our approach is the ability to model a subset of a given processor using a sub-automaton of the full execution model.<br /> Keyword: pipeline processing,Automata,automata theory,instruction sets,finite state automata,parallel finite automata,Synchronization,Program processors,instruction set,highly flexible synchronization scheme,Computational modeling,out-of-order execution,Hazards,parallel processing,Pipelines

U2 - 10.1109/NORCHIP.2010.5669478

DO - 10.1109/NORCHIP.2010.5669478

SN - 978-1-4244-8972-5

BT - NORCHIP, 2010

T2 - NORCHIP, 2010

SP - 1

EP - 4

ER -