Simulation is an indispensable tool for debugging and ver- ication of multicore systems. However simulation is slow. For complex multicore systems a simulation model will ex- ecute several orders of magnitude slower than the actual hardware implementation. We propose a method for cap- turing the hardware state of a multicore design while it is running on an FPGA. With minimal changes to the design and using only the built-in JTAG programming and debug- ging facilities, we describe how to transfer the state from an FPGA to a simulator. We also show how the state can be transferred back from the simulator to FPGA. Given that the design runs in real-time on the FPGA, the end result is speed improvements of orders of magnitude over traditional pure software simulation.