Easy simulation and design of on-chip inductors in standard CMOS processes

Publication: Research - peer-reviewArticle in proceedings – Annual report year: 1998

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This paper presents an approach to CMOS inductor modelling, that allow easy simulation in SPICE-like simulators. A number of test results are presented concerning optimal center hole, inductor area, wire spacing and self-inductance. Finally a comprehensive design guide is provided on how to design close-to-optimal inductors without the use of electromagnetic simulators
Original languageEnglish
Title of host publicationCircuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
Volume4
PublisherIEEE
Publication date1998
Pages360-364
ISBN (print)0-7803-4455-3
DOIs
StatePublished

Conference

Conference1998 IEEE International Symposium on Circuits and Systems
CountryUnited States
CityMonterey, CA
Period31/05/9803/06/98
Internet addresshttp://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=5627

Bibliographical note

Copyright: 1998 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

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