Design Principles for Synthesizable Processor Cores
Publication: Research - peer-review › Article in proceedings – Annual report year: 2012
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Design Principles for Synthesizable Processor Cores. / Schleuniger, Pascal; McKee, Sally A.; Karlsson, Sven .
In: Architecture of Computing Systems – ARCS 2012: 25th International Conference Munich, Germany, February 28 – March 2, 2012 Proceedings. Springer, 2012. p. 111-122 (Lecture Notes in Computer Science, Vol. 7179).Publication: Research - peer-review › Article in proceedings – Annual report year: 2012
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RIS
TY - GEN
T1 - Design Principles for Synthesizable Processor Cores
A1 - Schleuniger,Pascal
A1 - McKee,Sally A.
A1 - Karlsson,Sven
AU - Schleuniger,Pascal
AU - McKee,Sally A.
AU - Karlsson,Sven
PB - Springer
PY - 2012
Y1 - 2012
N2 - As FPGAs get more competitive, synthesizable processor cores become an attractive choice for embedded computing. Currently popular commercial processor cores do not fully exploit current FPGA architectures. In this paper, we propose general design principles to increase instruction throughput on FPGA-based processor cores: first, superpipelining enables higher-frequency system clocks, and second, predicated instructions circumvent costly pipeline stalls due to branches. To evaluate their effects, we develop Tinuso, a processor architecture optimized for FPGA implementation. We demonstrate through the use of micro-benchmarks that our principles guide the design of a processor core that improves performance by an average of 38% over a similar Xilinx MicroBlaze configuration.
AB - As FPGAs get more competitive, synthesizable processor cores become an attractive choice for embedded computing. Currently popular commercial processor cores do not fully exploit current FPGA architectures. In this paper, we propose general design principles to increase instruction throughput on FPGA-based processor cores: first, superpipelining enables higher-frequency system clocks, and second, predicated instructions circumvent costly pipeline stalls due to branches. To evaluate their effects, we develop Tinuso, a processor architecture optimized for FPGA implementation. We demonstrate through the use of micro-benchmarks that our principles guide the design of a processor core that improves performance by an average of 38% over a similar Xilinx MicroBlaze configuration.
KW - Synthesizable processor core
KW - FPGA
KW - Predication
KW - Pipelining
UR - http://www.arcs2012.tum.de/
U2 - 10.1007/978-3-642-28293-5_10
DO - 10.1007/978-3-642-28293-5_10
SN - 978-3-642-28292-8
BT - Architecture of Computing Systems – ARCS 2012
T2 - Architecture of Computing Systems – ARCS 2012
T3 - Lecture Notes in Computer Science
T3 - en_GB
SP - 111
EP - 122
ER -