Design Principles for Synthesizable Processor Cores

Publication: Research - peer-reviewArticle in proceedings – Annual report year: 2012

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As FPGAs get more competitive, synthesizable processor cores become an attractive choice for embedded computing. Currently popular commercial processor cores do not fully exploit current FPGA architectures. In this paper, we propose general design principles to increase instruction throughput on FPGA-based processor cores: first, superpipelining enables higher-frequency system clocks, and second, predicated instructions circumvent costly pipeline stalls due to branches. To evaluate their effects, we develop Tinuso, a processor architecture optimized for FPGA implementation. We demonstrate through the use of micro-benchmarks that our principles guide the design of a processor core that improves performance by an average of 38% over a similar Xilinx MicroBlaze configuration.
Original languageEnglish
Title of host publicationArchitecture of Computing Systems – ARCS 2012 : 25th International Conference Munich, Germany, February 28 – March 2, 2012 Proceedings
PublisherSpringer
Publication date2012
Pages111-122
ISBN (print)978-3-642-28292-8
ISBN (electronic)978-3-642-28293-5
DOIs
StatePublished

Conference

ConferenceARCS 2012 - Architecture of Computing Systems
Number25
CountryGermany
CityMünchen
Period28/02/1202/03/12
NameLecture Notes in Computer Science
Volume7179
ISSN (Print)0302-9743
CitationsWeb of Science® Times Cited: No match on DOI

Keywords

  • Synthesizable processor core, FPGA, Predication, Pipelining
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