Publication: Research - peer-review › Article in proceedings – Annual report year: 2012
As FPGAs get more competitive, synthesizable processor cores become an attractive choice for embedded computing. Currently popular commercial processor cores do not fully exploit current FPGA architectures. In this paper, we propose general design principles to increase instruction throughput on FPGA-based processor cores: first, superpipelining enables higher-frequency system clocks, and second, predicated instructions circumvent costly pipeline stalls due to branches. To evaluate their effects, we develop Tinuso, a processor architecture optimized for FPGA implementation. We demonstrate through the use of micro-benchmarks that our principles guide the design of a processor core that improves performance by an average of 38% over a similar Xilinx MicroBlaze configuration.
|Title of host publication||Architecture of Computing Systems – ARCS 2012 : 25th International Conference Munich, Germany, February 28 – March 2, 2012 Proceedings|
|State||Published - 2012|
|Event||ARCS 2012 - Architecture of Computing Systems - München, Germany|
|Conference||ARCS 2012 - Architecture of Computing Systems|
|Period||28/02/2012 → 02/03/2012|
|Name||Lecture Notes in Computer Science|
|Citations||Error in DOI please contact email@example.com|
- Synthesizable processor core, FPGA, Predication, Pipelining
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