Design of Networks-on-Chip for Real-Time Multi-Processor Systems-on-Chip

Publication: Research - peer-reviewArticle in proceedings – Annual report year: 2012

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This paper addresses the design of networks-on-chips for use in multi-processor systems-on-chips - the hardware platforms used in embedded systems. These platforms typically have to guarantee real-time properties, and as the network is a shared resource, it has to provide service guarantees (bandwidth and/or latency) to different communication flows. The paper reviews some past work in this field and the lessons learned, and the paper discusses ongoing research conducted as part of the project "Time-predictable Multi-Core Architecture for Embedded Systems" (T-CREST), supported by the European Commissions seventh framework programme. The aim of this project is to develop a general-purpose multi-core platform for real-time systems as well as tools supporting its use (compiler, simulator, and worst-case execution time analysis tool).
Original languageEnglish
Title of host publication2012 12th International Conference on Application of Concurrency to System Design (ACSD)
Number of pages5
PublisherIEEE
Publication date2012
ISBN (print)978-1-4673-1687-3
DOIs
StatePublished

Conference

Conference12th International Conference on Application of Concurrency to System Design (ACSD)
CountryGermany
CityHamburg
Period25/06/1229/06/12
Internet addresshttp://www.informatik.uni-hamburg.de/TGI/events/pn-acsd2012/home.shtml
NameInternational Conference on Application of Concurrency to System Design. Proceedings
ISSN (Print)1550-4808
CitationsWeb of Science® Times Cited: No match on DOI
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