Publication: Research - peer-review › Article in proceedings – Annual report year: 2011
Networks-on-Chip (NoCs) appeared as a strategy to deal with the communication requirements of complex IP-based System-on-Chips. As the complexity of designs increases and the technology scales down into the deep-submicron domain, the probability of malfunctions and failures in the NoC components increases. This paper focuses on the study and evaluation of techniques for increasing reliability and resilience of Network Interfaces (NIs). NIs act as interfaces between IP cores and the communication infrastructure; a faulty behavior in them could affect therefore the overall system. In this work, we propose a functional fault model for the NI components, and we present a two-level fault tolerant solution that can be employed for mitigating the effects of both single-event upset soft errors and hard errors on the NI. Experiments show that with a limited overhead we can obtain a significant reliability of the NI, while saving up to 83% in area with respect to a standard Triple Modular Redundancy implementation, as well as a significant energy reduction.
|Title of host publication||2011 14th Euromicro Conference on Digital System Design (DSD)|
|State||Published - 2011|
|Event||14th Euromicro Conference on Digital System Design - Oulu, Finland|
|Conference||14th Euromicro Conference on Digital System Design|
|Period||31/08/2011 → 02/09/2011|
|Citations||Web of Science® Times Cited: No match on DOI|
- Fault Tolerance, Systems-on-Chip, Networks-on-Chip, Network Interface
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