Publication: Research - peer-review › Article in proceedings – Annual report year: 1998
The basic algorithms underlying an automatic hardware synthesis environment using fully formal graphical requirements specifications as source language are outlined. The source language is real-time symbolic timing diagrams [FeyerabendJosko97], which are a metric-time temporal logic such that hard real-time constraints have to be dealt with. While automata-theoretic methods based on translating the specification to a finite automaton and constructing a winning strategy in the resulting omega-regular game could in principle be used, and do indeed provide the core algorithm, complexity withstands practical application of these methods. Therefore, a compositional extension is explored, which yields modular synthesis of multi-component controllers. Based on this, a second extension is proposed for efficiently dealing with hard real-time constraints.
|Title of host publication||Formal Techniques in Real-Time and Fault-Tolerant Systems. 5th International Symposium, FTRTFT'98. Proceedings|
|ISBN (print)||3 540 65003 2|
|Conference||5th International Symposium Formal Techniques in Real-Time and Fault-Tolerant Systems|
|Period||14/09/98 → 18/09/98|
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