Behavioral Synthesis of Asynchronous Circuits Using Syntax Directed Translation as Backend

Publication: Research - peer-review › Journal article – Annual report year: 2009

Standard

Behavioral Synthesis of Asynchronous Circuits Using Syntax Directed Translation as Backend. / Nielsen, Sune Fallgaard ; Sparsø, Jens ; Madsen, Jan.

In: IEEE Transactions on Very Large Scale Integration Systems, Vol. 17, No. 2, 2009, p. 248-261.

Publication: Research - peer-review › Journal article – Annual report year: 2009

Publication: Research - peer-review › Journal article – Annual report year: 2009

Bibtex

@article{b04ae1b3034d4e1dab584e6f649fcbb0,

title = "Behavioral Synthesis of Asynchronous Circuits Using Syntax Directed Translation as Backend",

publisher = "I E E E",

author = "Nielsen, {Sune Fallgaard} and Jens Sparsø and Jan Madsen",

note = "{"}©2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.{"}",

year = "2009",

volume = "17",

number = "2",

pages = "248--261",

journal = "IEEE Transactions on Very Large Scale Integration Systems",

issn = "1063-8210",

}

RIS

TY - JOUR

T1 - Behavioral Synthesis of Asynchronous Circuits Using Syntax Directed Translation as Backend

A1 - Nielsen,Sune Fallgaard

A1 - Sparsø,Jens

A1 - Madsen,Jan

AU - Nielsen,Sune Fallgaard

AU - Sparsø,Jens

AU - Madsen,Jan

PB - I E E E

PY - 2009

Y1 - 2009

N2 - The current state-of-the art in high-level synthesis of asynchronous circuits is syntax directed translation, which performs a one-to-one mapping of a HDL-description into a corresponding circuit. This paper presents a method for behavioral synthesis of asynchronous circuits which builds on top of syntax directed translation, and which allows the designer to perform automatic design space exploration guided by area or speed constraints. The paper presents an asynchronous implementation template consisting of a data-path and a control unit and its implementation using the asynchronous hardware description language Balsa [1]. This ”conventional” template architecture allows us to adapt traditional synchronous synthesis techniques for resource sharing, scheduling, binding etc, to the domain of asynchronous circuits. A prototype tool has been implemented on top of the Balsa framework, and the method is illustrated through the implementation of a set of example circuits. The main contributions of the paper are: the fundamental idea, the template architecture and its implementation using asynchronous handshake components, and the implementation of a prototype tool.

AB - The current state-of-the art in high-level synthesis of asynchronous circuits is syntax directed translation, which performs a one-to-one mapping of a HDL-description into a corresponding circuit. This paper presents a method for behavioral synthesis of asynchronous circuits which builds on top of syntax directed translation, and which allows the designer to perform automatic design space exploration guided by area or speed constraints. The paper presents an asynchronous implementation template consisting of a data-path and a control unit and its implementation using the asynchronous hardware description language Balsa [1]. This ”conventional” template architecture allows us to adapt traditional synchronous synthesis techniques for resource sharing, scheduling, binding etc, to the domain of asynchronous circuits. A prototype tool has been implemented on top of the Balsa framework, and the method is illustrated through the implementation of a set of example circuits. The main contributions of the paper are: the fundamental idea, the template architecture and its implementation using asynchronous handshake components, and the implementation of a prototype tool.

U2 - 10.1109/TVLSI.2008.2005285

DO - 10.1109/TVLSI.2008.2005285

JO - IEEE Transactions on Very Large Scale Integration Systems

JF - IEEE Transactions on Very Large Scale Integration Systems

SN - 1063-8210

IS - 2

VL - 17

SP - 248

EP - 261

ER -