Area-Efficiency Trade-Offs in Integrated Switched-Capacitor DC-DC Converters

Research output: Research - peer-reviewArticle in proceedings – Annual report year: 2016

View graph of relations

This paper analyzes the relationship between efficiency and chip area in a fully integrated switched capacitor voltage divider dc-dc converter implemented in 180nm-technology and a 1/2 topology. A numerical algorithm for choosing the optimal sizes of individual components, in terms of power loss, based on the total chip area is developed. This algorithm also determines the optimal number of parallel phases in the converter, based on an estimate of power consumption in flip-
flop based clock circuits. By these means the maximum achievable efficiency as a function of chip area is estimated
Original languageEnglish
Title of host publicationProceedings of NORCAS 2016
Number of pages5
PublisherIEEE
Publication date2016
ISBN (Print)978-1-5090-1095-0
DOIs
StatePublished - 2016
Event2016 IEEE NorCAS Conference - Copenhagen, Denmark
Duration: 1 Nov 20162 Nov 2016

Conference

Conference2016 IEEE NorCAS Conference
CountryDenmark
CityCopenhagen
Period01/11/201602/11/2016
CitationsWeb of Science® Times Cited: No match on DOI
Download as:
Download as PDF
Select render style:
APAAuthorCBE/CSEHarvardMLAStandardVancouverShortLong
PDF
Download as HTML
Select render style:
APAAuthorCBE/CSEHarvardMLAStandardVancouverShortLong
HTML
Download as Word
Select render style:
APAAuthorCBE/CSEHarvardMLAStandardVancouverShortLong
Word

ID: 127045832