Publication: Research - peer-review › Conference article – Annual report year: 2003
In this paper, a low noise high gain CMOS amplifier for minute nerve signals is presented. The amplifier is constructed in a fully differential topology to maximize noise rejection. By using a mixture of weak- and strong inversion transistors, optimal noise suppression in the amplifier is achieved. A continuous-time current-steering offset-compensation technique is utilized in order to minimize the noise contribution and to minimize dynamic impact on the amplifier input nodes. The method for signal recovery from noisy nerve signals is presented. A prototype amplifier is realized in a standard digital 0.5 mum CMOS single poly, n-well process. The prototype amplifier features a gain of 80 dB over a 10 kHz bandwidth, a CMRR of more than 87 dB and a PSRR greater than 84 dB. The equivalent input referred noise in the bandwidth of interest is 4.8 nV/rootHz. The amplifier power consumption is 275 muW, drawn from a power supply; V-DD = -V-SS = 1.5 V.
|Journal||Analog Integrated Circuits and Signal Processing|
|Conference||8th IEEE International Conference on Electronics, Circuits and Systems|
|Period||02/09/01 → 05/09/01|
|Sponsor||IEEE CAS; MALTACOM; Air Malta; MITTS; Univ Malta|
|Citations||Web of Science® Times Cited: 8|
- Neural sensor, implantable microsystems, FES, ENG
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