An Area-Efficient TDM NoC Supporting Reconfiguration for Mode Changes

Publication: Research - peer-reviewArticle in proceedings – Annual report year: 2016

Standard

An Area-Efficient TDM NoC Supporting Reconfiguration for Mode Changes. / Sørensen, Rasmus Bo; Pezzarossa, Luca; Sparsø, Jens.

Proceedings of the 10th IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2016). IEEE, 2016.

Publication: Research - peer-reviewArticle in proceedings – Annual report year: 2016

Harvard

Sørensen, RB, Pezzarossa, L & Sparsø, J 2016, An Area-Efficient TDM NoC Supporting Reconfiguration for Mode Changes. in Proceedings of the 10th IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2016). IEEE. DOI: 10.1109/NOCS.2016.7579324

APA

Sørensen, R. B., Pezzarossa, L., & Sparsø, J. (2016). An Area-Efficient TDM NoC Supporting Reconfiguration for Mode Changes. In Proceedings of the 10th IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2016) IEEE. DOI: 10.1109/NOCS.2016.7579324

CBE

Sørensen RB, Pezzarossa L, Sparsø J. 2016. An Area-Efficient TDM NoC Supporting Reconfiguration for Mode Changes. In Proceedings of the 10th IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2016). IEEE. Available from: 10.1109/NOCS.2016.7579324

MLA

Sørensen, Rasmus Bo, Luca Pezzarossa, and Jens Sparsø "An Area-Efficient TDM NoC Supporting Reconfiguration for Mode Changes". Proceedings of the 10th IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2016). IEEE. 2016. Available: 10.1109/NOCS.2016.7579324

Vancouver

Sørensen RB, Pezzarossa L, Sparsø J. An Area-Efficient TDM NoC Supporting Reconfiguration for Mode Changes. In Proceedings of the 10th IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2016). IEEE. 2016. Available from, DOI: 10.1109/NOCS.2016.7579324

Author

Sørensen, Rasmus Bo; Pezzarossa, Luca; Sparsø, Jens / An Area-Efficient TDM NoC Supporting Reconfiguration for Mode Changes.

Proceedings of the 10th IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2016). IEEE, 2016.

Publication: Research - peer-reviewArticle in proceedings – Annual report year: 2016

Bibtex

@inbook{923b9b117cc04d16a977033d87bd3a3a,
title = "An Area-Efficient TDM NoC Supporting Reconfiguration for Mode Changes",
abstract = "This paper presents an area-efficient time-division-multiplexing (TDM) network-on-chip (NoC) intended for use in a multicore platform for hard real-time systems. In such a platform, a mode change at the application level requires the tear-down and set-up of some virtual circuits without affecting the virtual circuits that persist across the mode change. Our NoC supports such reconfiguration in a very efficient way, using the same resources that are used for transmission of regular data. We evaluate the presented NoC in terms of worst-case reconfiguration time, hardware cost, and maximum operating frequency. The results show that the hardware cost for an FPGA implementation of our architecture is a factor of 2.2 to 3.9 times smaller than other NoCs with reconfiguration functionalities, and that the worst-case time for a reconfiguration is shorter or comparable to those NoCs.",
author = "Sørensen, {Rasmus Bo} and Luca Pezzarossa and Jens Sparsø",
year = "2016",
doi = "10.1109/NOCS.2016.7579324",
isbn = "978-1-4673-9030-9",
booktitle = "Proceedings of the 10th IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2016)",
publisher = "IEEE",

}

RIS

TY - GEN

T1 - An Area-Efficient TDM NoC Supporting Reconfiguration for Mode Changes

AU - Sørensen,Rasmus Bo

AU - Pezzarossa,Luca

AU - Sparsø,Jens

PY - 2016

Y1 - 2016

N2 - This paper presents an area-efficient time-division-multiplexing (TDM) network-on-chip (NoC) intended for use in a multicore platform for hard real-time systems. In such a platform, a mode change at the application level requires the tear-down and set-up of some virtual circuits without affecting the virtual circuits that persist across the mode change. Our NoC supports such reconfiguration in a very efficient way, using the same resources that are used for transmission of regular data. We evaluate the presented NoC in terms of worst-case reconfiguration time, hardware cost, and maximum operating frequency. The results show that the hardware cost for an FPGA implementation of our architecture is a factor of 2.2 to 3.9 times smaller than other NoCs with reconfiguration functionalities, and that the worst-case time for a reconfiguration is shorter or comparable to those NoCs.

AB - This paper presents an area-efficient time-division-multiplexing (TDM) network-on-chip (NoC) intended for use in a multicore platform for hard real-time systems. In such a platform, a mode change at the application level requires the tear-down and set-up of some virtual circuits without affecting the virtual circuits that persist across the mode change. Our NoC supports such reconfiguration in a very efficient way, using the same resources that are used for transmission of regular data. We evaluate the presented NoC in terms of worst-case reconfiguration time, hardware cost, and maximum operating frequency. The results show that the hardware cost for an FPGA implementation of our architecture is a factor of 2.2 to 3.9 times smaller than other NoCs with reconfiguration functionalities, and that the worst-case time for a reconfiguration is shorter or comparable to those NoCs.

U2 - 10.1109/NOCS.2016.7579324

DO - 10.1109/NOCS.2016.7579324

M3 - Article in proceedings

SN - 978-1-4673-9030-9

BT - Proceedings of the 10th IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2016)

PB - IEEE

ER -