An Area-Efficient TDM NoC Supporting Reconfiguration for Mode Changes

Publication: Research - peer-reviewArticle in proceedings – Annual report year: 2016

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This paper presents an area-efficient time-division-multiplexing (TDM) network-on-chip (NoC) intended for use in a multicore platform for hard real-time systems. In such a platform, a mode change at the application level requires the tear-down and set-up of some virtual circuits without affecting the virtual circuits that persist across the mode change. Our NoC supports such reconfiguration in a very efficient way, using the same resources that are used for transmission of regular data. We evaluate the presented NoC in terms of worst-case reconfiguration time, hardware cost, and maximum operating frequency. The results show that the hardware cost for an FPGA implementation of our architecture is a factor of 2.2 to 3.9 times smaller than other NoCs with reconfiguration functionalities, and that the worst-case time for a reconfiguration is shorter or comparable to those NoCs.
Original languageEnglish
Title of host publicationProceedings of the 10th IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2016)
Number of pages4
PublisherIEEE
Publication date2016
ISBN (print)978-1-4673-9030-9
DOIs
StatePublished - 2016
Event10th IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2016) - Nara, Japan

Conference

Conference10th IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2016)
Number10
CountryJapan
CityNara
Period31/08/201602/09/2016
Internet address
CitationsWeb of Science® Times Cited: No match on DOI
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