Publication: Research - peer-review › Article in proceedings – Annual report year: 2012
This paper explores the design of a circuit-switched network-on-chip (NoC) based on time-division-multiplexing (TDM) for use in hard real-time systems. Previous work has primarily considered application-specific systems. The work presented here targets general-purpose hardware platforms. We consider a system with IP-cores, where the TDM-NoC must provide directed virtual circuits - all with the same bandwidth - between all nodes. This may not be a frequent scenario, but a general platform should provide this capability, and it is an interesting point in the design space to study. The paper presents an FPGA-friendly hardware design, which is simple, fast, and consumes minimal resources. Furthermore, an algorithm to find minimum-period schedules for all-to-all virtual circuits on top of typical physical NoC topologies like 2D-mesh, torus, bidirectional torus, tree, and fat-tree is presented. The static schedule makes the NoC time-predictable and enables worst-case execution time analysis of communicating real-time tasks.
|Title of host publication||2012 Sixth IEEE/ACM International Symposium on Networks on Chip (NoCS)|
|Conference||6th ACM/IEEE International Symposium on Networks-on-Chip|
|Period||09/05/12 → 11/05/12|
|Citations||Web of Science® Times Cited: No match on DOI|
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