Publication: Research - peer-review › Journal article – Annual report year: 2005
A novel method to calibrate the frequency response of a Phase-Locked Loop is presented. The method requires just an additional digital counter to measure the natural frequency of the PLL; moreover it is capable of estimating the static phase offset. The measured value can be used to tune the PLL response to the desired value. The method is demonstrated mathematically on a typical PLL topology and it is extended to SigmaDelta fractional-N PLLs. A set of simulations performed with two different simulators is used to verify the applicability of the method.
|Journal||Analog Integrated Circuits and Signal Processing|
|Citations||Web of Science® Times Cited: 0|