A new architecture for a single-chip multi-channel beamformer based on a standard FPGA

Publication: Research - peer-reviewArticle in proceedings – Annual report year: 2001

Standard

A new architecture for a single-chip multi-channel beamformer based on a standard FPGA. / Tomov, Borislav Gueorguiev; Jensen, Jørgen Arendt.

Proceedings of IEEE Ultrasonics Symposium. Vol. 2 IEEE, 2001. p. 1529-1533.

Publication: Research - peer-reviewArticle in proceedings – Annual report year: 2001

Harvard

APA

CBE

Tomov BG, Jensen JA. 2001. A new architecture for a single-chip multi-channel beamformer based on a standard FPGA. In Proceedings of IEEE Ultrasonics Symposium. IEEE. pp. 1529-1533. Available from: 10.1109/ULTSYM.2001.992011

MLA

Vancouver

Tomov BG, Jensen JA. A new architecture for a single-chip multi-channel beamformer based on a standard FPGA. In Proceedings of IEEE Ultrasonics Symposium. Vol. 2. IEEE. 2001. p. 1529-1533. Available from: 10.1109/ULTSYM.2001.992011

Author

Tomov, Borislav Gueorguiev; Jensen, Jørgen Arendt / A new architecture for a single-chip multi-channel beamformer based on a standard FPGA.

Proceedings of IEEE Ultrasonics Symposium. Vol. 2 IEEE, 2001. p. 1529-1533.

Publication: Research - peer-reviewArticle in proceedings – Annual report year: 2001

Bibtex

@inbook{a6dfdf9586764e88a291568a25e612c0,
title = "A new architecture for a single-chip multi-channel beamformer based on a standard FPGA",
publisher = "IEEE",
author = "Tomov, {Borislav Gueorguiev} and Jensen, {Jørgen Arendt}",
year = "2001",
doi = "10.1109/ULTSYM.2001.992011",
volume = "2",
isbn = "0-7803-7177-1",
pages = "1529-1533",
booktitle = "Proceedings of IEEE Ultrasonics Symposium",

}

RIS

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T1 - A new architecture for a single-chip multi-channel beamformer based on a standard FPGA

A1 - Tomov,Borislav Gueorguiev

A1 - Jensen,Jørgen Arendt

AU - Tomov,Borislav Gueorguiev

AU - Jensen,Jørgen Arendt

PB - IEEE

PY - 2001

Y1 - 2001

N2 - A new architecture for a compact medical ultrasound beamformer has been developed. Combination of novel and known principles has been utilized, leading to low processing power requirements and simple analog circuitry. Usage of a field programmable gate array (FPGA) for the digital signal processing provides programming flexibility. First, sparse sample processing is performed by generating the in-phase and quadrature beamformed signals. Hereby only 512 samples are beamformed for each line in an image. That leads to a 15-fold decrease in the number of operations and enables the use of Delta-Sigma (ΔΣ) modulation analog-to-digital converters (ADC). Second, simple second-order ΔΣ modulation ADC with classic topology is used. This allows for simple analog circuitry and a very compact design. Several tens of these together with the corresponding preamplifiers can be fitted together onto a single analog integrated circuit. Third, parameter driven delay generation is used, using 3 input parameters per line per channel for either linear array imaging or phased array imaging. The delays are generated on the fly. The delay generation logic also determines the digital apodization by using 2 additional parameters. The control logic consists of few adders and counters and requires very limited resources. Fourth, the beamformer is fully programmable. Any channel can be set to use an arbitrary delay curve, and any number of these channels can be used together in an extendable modular multi-channel system. A prototype of the digital logic is implemented using a Xilinx Virtex-E series FPGA. A 5 MHz center frequency is used along with an oversampling ratio of 14. The sampling clock frequency used is 140 MHz and the number of channels in a single Xilinx 1 million gate FPGA XCV600E is 32. The beamformer utilizes all of the BlockRAM of the device and 33% of its Core Logic Block (CLB) resources. Both simulation results and processed echo data from a phantom are presented.

AB - A new architecture for a compact medical ultrasound beamformer has been developed. Combination of novel and known principles has been utilized, leading to low processing power requirements and simple analog circuitry. Usage of a field programmable gate array (FPGA) for the digital signal processing provides programming flexibility. First, sparse sample processing is performed by generating the in-phase and quadrature beamformed signals. Hereby only 512 samples are beamformed for each line in an image. That leads to a 15-fold decrease in the number of operations and enables the use of Delta-Sigma (ΔΣ) modulation analog-to-digital converters (ADC). Second, simple second-order ΔΣ modulation ADC with classic topology is used. This allows for simple analog circuitry and a very compact design. Several tens of these together with the corresponding preamplifiers can be fitted together onto a single analog integrated circuit. Third, parameter driven delay generation is used, using 3 input parameters per line per channel for either linear array imaging or phased array imaging. The delays are generated on the fly. The delay generation logic also determines the digital apodization by using 2 additional parameters. The control logic consists of few adders and counters and requires very limited resources. Fourth, the beamformer is fully programmable. Any channel can be set to use an arbitrary delay curve, and any number of these channels can be used together in an extendable modular multi-channel system. A prototype of the digital logic is implemented using a Xilinx Virtex-E series FPGA. A 5 MHz center frequency is used along with an oversampling ratio of 14. The sampling clock frequency used is 140 MHz and the number of channels in a single Xilinx 1 million gate FPGA XCV600E is 32. The beamformer utilizes all of the BlockRAM of the device and 33% of its Core Logic Block (CLB) resources. Both simulation results and processed echo data from a phantom are presented.

U2 - 10.1109/ULTSYM.2001.992011

DO - 10.1109/ULTSYM.2001.992011

SN - 0-7803-7177-1

VL - 2

BT - Proceedings of IEEE Ultrasonics Symposium

T2 - Proceedings of IEEE Ultrasonics Symposium

SP - 1529

EP - 1533

ER -