A new architecture for a single-chip multi-channel beamformer based on a standard FPGA

Publication: Research - peer-reviewArticle in proceedings – Annual report year: 2001

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A new architecture for a compact medical ultrasound beamformer has been developed. Combination of novel and known principles has been utilized, leading to low processing power requirements and simple analog circuitry. Usage of a field programmable gate array (FPGA) for the digital signal processing provides programming flexibility. First, sparse sample processing is performed by generating the in-phase and quadrature beamformed signals. Hereby only 512 samples are beamformed for each line in an image. That leads to a 15-fold decrease in the number of operations and enables the use of Delta-Sigma (ΔΣ) modulation analog-to-digital converters (ADC). Second, simple second-order ΔΣ modulation ADC with classic topology is used. This allows for simple analog circuitry and a very compact design. Several tens of these together with the corresponding preamplifiers can be fitted together onto a single analog integrated circuit. Third, parameter driven delay generation is used, using 3 input parameters per line per channel for either linear array imaging or phased array imaging. The delays are generated on the fly. The delay generation logic also determines the digital apodization by using 2 additional parameters. The control logic consists of few adders and counters and requires very limited resources. Fourth, the beamformer is fully programmable. Any channel can be set to use an arbitrary delay curve, and any number of these channels can be used together in an extendable modular multi-channel system. A prototype of the digital logic is implemented using a Xilinx Virtex-E series FPGA. A 5 MHz center frequency is used along with an oversampling ratio of 14. The sampling clock frequency used is 140 MHz and the number of channels in a single Xilinx 1 million gate FPGA XCV600E is 32. The beamformer utilizes all of the BlockRAM of the device and 33% of its Core Logic Block (CLB) resources. Both simulation results and processed echo data from a phantom are presented.
Original languageEnglish
Title of host publicationProceedings of IEEE Ultrasonics Symposium
Volume2
PublisherIEEE
Publication date2001
Pages1529-1533
ISBN (print)0-7803-7177-1
DOIs
StatePublished

Conference

Conference2001 IEEE Ultrasonics Symposium
CountryUnited States
CityAtlanta, GA
Period07/10/0110/10/01
Internet addresshttp://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=7781

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Copyright: 2000 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

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