A Controller for Dynamic Partial Reconfiguration in FPGA-Based Real-Time Systems

Publication: Research - peer-reviewArticle in proceedings – Annual report year: 2017


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In real-time systems, the use of hardware accelerators can lead to a worst-case execution-time speed-up, to a simplification of its analysis, and to a reduction of its pessimism. When using FPGA technology, dynamic partial reconfiguration (DPR) can be used to minimize the area, by only loading those accelerators that are needed at any given point in time. The DPR controllers provided by the FPGA vendors satisfy a wide range of requirements and rely on software to manage the reconfiguration. This approach may lead to slow reconfiguration and unpredictable timing. This paper presents an open-source DPR controller specially developed for hard real-time systems and prototyped in connection with the open-source multi-core platform for real-time applications T-CREST. The controller enables a processor to perform reconfiguration in a time-predictable manner and supports different operating modes. The paper also presents a software tool for bitstream conversion, compression, and for reconfiguration time analysis. The DPR controller is evaluated in terms of hardware cost, operating frequency, speed, and bitstream compression ratio vs. reconfiguration time trade-off. A simple application example is also presented with the scope of showing the reconfiguration features of the controller.
Original languageEnglish
Title of host publication2017 IEEE 20th International Symposium on Real-Time Distributed Computing
Publication date2017
StatePublished - 2017
Event2017 IEEE 20th International Symposium on Real-Time Distributed Computing - Toronto, Canada


Conference2017 IEEE 20th International Symposium on Real-Time Distributed Computing
LocationFields Institute
Series2017 Ieee 20th International Symposium on Real-time Distributed Computing (isorc). Proceedings
CitationsWeb of Science® Times Cited: 1


  • Logic circuits, Logic and switching circuits, Field programmable gate arrays, Real-time systems, Dynamic partial reconfiguration, FPGA-based real-time systems, Open-source DPR controller, Open-source multicore platform, Software tool, Hardware, Process control, Computer architecture, Software, Random access memory, Reconfiguration controller, Reconfiguration time analysis, T-CREST multi-core platform, Reconfiguration application example
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ID: 134333066